Datasheet4U Logo Datasheet4U.com

IS43LR32320C - 1Gb Mobile DDR SDRAM

This page provides the datasheet information for the IS43LR32320C, a member of the IS46LR32320C 1Gb Mobile DDR SDRAM family.

Datasheet Summary

Description

The IS43/46LR16640C/32320C is 1,073,741,824 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 64Meg words of 16bits or 32Meg words of 32bits.

This product uses a double-data-rate architecture to achieve high-speed operation.

Features

  • JEDEC standard 1.8V power supply.
  • VDD = 1.8V, VDDQ = 1.8V.
  • Four internal banks for concurrent operation.
  • MRS cycle with address key programs - CAS latency 2, 3 (clock) - Burst length (2, 4, 8, 16) - Burst type (sequential & interleave).
  • Fully differential clock inputs (CK, /CK).
  • All inputs except data & DM are sampled at the rising edge of the system clock.
  • Data I/O transaction on both edges of data strobe.
  • Bidirectional d.

📥 Download Datasheet

Datasheet preview – IS43LR32320C

Datasheet Details

Part number IS43LR32320C
Manufacturer ISSI
File Size 1.19 MB
Description 1Gb Mobile DDR SDRAM
Datasheet download datasheet IS43LR32320C Datasheet
Additional preview pages of the IS43LR32320C datasheet.
Other Datasheets by ISSI

Full PDF Text Transcription

Click to expand full text
IS43/46LR32320C IS43/46LR16640C 1Gb (x16, x32) Mobile DDR SDRAM Description Preliminary Information OCTOBER 2022 The IS43/46LR16640C/32320C is 1,073,741,824 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 4 banks of 64Meg words of 16bits or 32Meg words of 32bits. This product uses a double-data-rate architecture to achieve high-speed operation. The Data Input/ Output signals are transmitted on a 16-bit or 32-bit bus. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock.
Published: |