IS43LR16200D Datasheet PDF - ISSI 1M x 16Bits x 2Banks Mobile DDR SDRAM Specs

IS43LR16200D - 1M x 16Bits x 2Banks Mobile DDR SDRAM

This page provides the datasheet information for the IS43LR16200D, a member of the IS46LR16200D 1M x 16Bits x 2Banks Mobile DDR SDRAM family.

Datasheet Summary

Description

The IS43LR16200D is 33,554,432 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 2 banks of 1,048,576 words x 16 bits.

This product uses a double-data-rate architecture to achieve high-speed operation.

Features

JEDEC standard 1.8V power supply.
Two internal banks for concurrent operation.
MRS cycle with address key programs - CAS latency 2, 3 (clock) - Burst length (2, 4, 8, 16) - Burst type (sequential & interleave).
Fully differential clock inputs (CK, /CK).
All inputs except data & DM are sampled at the rising edge of the system clock.
Data I/O transaction on both edges of data strobe.
Bidirectional data strobe per byte of data (DQS).

Datasheet Details

Part number	IS43LR16200D
Manufacturer	ISSI
File Size	1.72 MB
Description	1M x 16Bits x 2Banks Mobile DDR SDRAM
Datasheet	IS43LR16200D Datasheet
Additional preview pages of the IS43LR16200D datasheet.

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Full PDF Text Transcription

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IS43/46LR16200D 1M x 16Bits x 2Banks Mobile DDR SDRAM Description The IS43LR16200D is 33,554,432 bits CMOS Mobile Double Data Rate Synchronous DRAM organized as 2 banks of 1,048,576 words x 16 bits. This product uses a double-data-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2N prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. This product offers fully synchronous operations referenced to both rising and falling edges of the clock. The data paths are internally pipelined and 2n-bits prefetched to achieve high bandwidth. All input and output voltage levels are compatible with LVCMOS. Features • JEDEC standard 1.

Published: Jun 28, 2016 |