IS43DR16320D - DDR2 DRAM

Datasheet Summary

Description

ISSI's 512Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation.

The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.

Features

Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V.
JEDEC standard 1.8V I/O (SSTL_18-compatible).
Double data rate interface: two data transfers per clock cycle.
Differential data strobe (DQS, DQS).
4-bit prefetch architecture.
On chip DLL to align DQ and DQS transitions with CK.
4 internal banks for concurrent operation.
Programmable CAS latency (CL) 3, 4, 5, and 6 supported.
Posted CAS and programmable additive latency (AL) 0,.

ISSI

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Datasheet Details

Part number	IS43DR16320D
Manufacturer	ISSI
File Size	1.07 MB
Description	DDR2 DRAM
Datasheet	IS43DR16320D Datasheet
Additional preview pages of the IS43DR16320D datasheet.

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Full PDF Text Transcription

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IS43/46DR86400D IS43/46DR16320D 64Mx8, 32Mx16 DDR2 DRAM FEATURES • Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V • JEDEC standard 1.

Published: Aug 1, 2016 |