Datasheet4U Logo Datasheet4U.com

IN74LS164 - 8-Bit Parallel-Out Shift Register

Features

  • gated serial inputs and an asynchronous reset. The gated serial inputs (A and B) permit complete control over incoming data as a low at either (or both) input(s) inhibits entry of the new data and resets the first flip flop to the low level at the next clock pulse. A high level input enables the other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only information meeting the setup requirements will b.

📥 Download Datasheet

Datasheet Details

Part number IN74LS164
Manufacturer IK Semiconductor
File Size 280.89 KB
Description 8-Bit Parallel-Out Shift Register
Datasheet download datasheet IN74LS164 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
IN74LS07 Hex Non-Inverted Buffers with Open- Collector Outputs ETC
IN74LS07D Hex Non-Inverted Buffers with Open- Collector Outputs ETC
IN74LS07N Hex Non-Inverted Buffers with Open- Collector Outputs ETC
IN74LS240AN OCTAL BUFFER / DRIVER WITH 3-STATE OUTPUTS ETC
IN746A Half Watt Zeners Fairchild Semiconductor

Other Datasheets by IK Semiconductor

Part Number Description
IN74LS161 4-Bit Binary Counter
IN74LS138 3-8 Decoder/Demultiplexer
IN74LS14 Hex Schmitt-Trigger Inverter
IN74LS157 Quad 2-1 Data Selector/Multiplexer
IN74LS04 Hex Inverter

Full PDF Text Transcription

Click to expand full text
TECHNICAL DATA IN74LS164 8-Bit Serial-Input/Parallel-Output Shift Register This 8-bit shift register features gated serial inputs and an asynchronous reset. The gated serial inputs (A and B) permit complete control over incoming data as a low at either (or both) input(s) inhibits entry of the new data and resets the first flip flop to the low level at the next clock pulse. A high level input enables the other input which will then determine the state of the first flip-flop. Data at the serial inputs may be changed while the clock is high or low, but only information meeting the setup requirements will be entered clocking occurs or the low-to-high level transition of the clock input. All inputs are diode-clamped to minimize transmission-line effects.
Published: |