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IDT54AHCT640 - High Speed CMOS Octal Inverting Buffer Transceiver

Download the IDT54AHCT640 datasheet PDF. This datasheet also covers the IDT74AHCT640 variant, as both devices belong to the same high speed cmos octal inverting buffer transceiver family and are provided as variant models within a single manufacturer datasheet.

Description

The IDT54/74AHCT640 are 8-bit inverting buffer transceivers built using advanced CEMOS'", a dual metal CMOS technology.

These octal bus transceivers are designed for asynchronous two-way communication between data buses.

Features

  • Equivalent to ALS speeds and output drive over full temperature and voltage supply extremes.
  • 10ns data to output.
  • IOl = 14mA over full military temperature range.
  • CMOS power levels (5p. W typo static).
  • 80th CMOS and TTL output compatible.
  • Substantially lower input current levels than ALS (5p. A max. ).
  • Inverting buffer transceiver.
  • 100% product assurance screening to MIL-STD-883, Class 8 is available.
  • JEDEC standard.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (IDT74AHCT640-IDT.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number IDT54AHCT640
Manufacturer IDT
File Size 168.41 KB
Description High Speed CMOS Octal Inverting Buffer Transceiver
Datasheet download datasheet IDT54AHCT640 Datasheet

Full PDF Text Transcription

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FEATURES: • Equivalent to ALS speeds and output drive over full temperature and voltage supply extremes • 10ns data to output • IOl = 14mA over full military temperature range • CMOS power levels (5p.W typo static) • 80th CMOS and TTL output compatible • Substantially lower input current levels than ALS (5p.A max.) • Inverting buffer transceiver • 100% product assurance screening to MIL-STD-883, Class 8 is available • JEDEC standard pinout for DIP and LCC DESCRIPTION: The IDT54/74AHCT640 are 8-bit inverting buffer transceivers built using advanced CEMOS'", a dual metal CMOS technology. These octal bus transceivers are designed for asynchronous two-way communication between data buses.
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