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8735-31 - Differential-to-3.3V LVPECL Zero Delay Clock Generator

Datasheet Summary

Description

The 8735-31 is a highly versatile 1:5 Differential -to-3.3V LVPECL Clock Generator.

The 8735-31 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 15.625MHz to 350MHz.

Features

  • Five differential 3.3V LVPECL output pairs.
  • Selectable differential clock inputs.
  • CLKx/nCLKx pairs can accept the following differential input level.

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Datasheet Details

Part number 8735-31
Manufacturer IDT
File Size 267.50 KB
Description Differential-to-3.3V LVPECL Zero Delay Clock Generator
Datasheet download datasheet 8735-31 Datasheet
Additional preview pages of the 8735-31 datasheet.

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Full PDF Text Transcription

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1:5, Differential-to-3.3V LVPECL Zero Delay Clock Generator 8735-31 Data Sheet General Description The 8735-31 is a highly versatile 1:5 Differential -to-3.3V LVPECL Clock Generator. The 8735-31 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider, and has an output frequency range of 15.625MHz to 350MHz. The reference divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external feedback allows the device to achieve “zero delay” between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes.
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