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ICS558-02 - LVHSTL TO CMOS CLOCK DIVIDER

Description

The ICS558-02 accepts a high-speed LVHSTL input and provides four CMOS low skew outputs from a selectable internal divider (divide by 3, divide by 4).

The four outputs are split into two banks of two outputs.

Each bank has a separate output enable to tri-state the output buffers.

Features

  • 16-pin TSSOP package LVHSTL inputs Accepts up to 250 MHz input frequency Four low skew (.

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Datasheet Details

Part number ICS558-02
Manufacturer ICST
File Size 146.40 KB
Description LVHSTL TO CMOS CLOCK DIVIDER
Datasheet download datasheet ICS558-02 Datasheet

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www.DataSheet4U.com ICS558-02 LVHSTL TO CMOS CLOCK DIVIDER Description The ICS558-02 accepts a high-speed LVHSTL input and provides four CMOS low skew outputs from a selectable internal divider (divide by 3, divide by 4). The four outputs are split into two banks of two outputs. Each bank has a separate output enable to tri-state the output buffers. The ICS558-02 is a member of the ICS Clock BlocksTM family of clock generation, synchronization, and distribution devices. Features • • • • • • 16-pin TSSOP package LVHSTL inputs Accepts up to 250 MHz input frequency Four low skew (<250 ps) outputs Selectable internal divider of 3 or 4 Operating voltage of 3.
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