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HY5PS121621CFP - DDR2 SDRAM

General Description

and is subject to change without notice.

Hynix Semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Key Features

  • and Ordering Information 1.1.1 Key Feaures 1.1.2 Ordering Information 1.2 Pin configuration 32M °ø16 DDR2 Pin Configuration 1.3 Pin.

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HY5PS121621CFP 512Mb(32Mx16) DDR2 SDRAM HY5PS121621CFP This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.3/ Feb. 2007 1 Free Datasheet http://www.datasheet4u.net/ 1HY5PS121621CFP Revision Details Revision No. 0.1 Defined target spec. Added Idd values, changed from VDD(Q)=2.1V to VDD(Q)=2.0V, CL from 3 to 7 is supported and removed Default Output V-I characteristics (page 63, 64 and 65 on Rev.0.1). 1. Changed number(0.30mV --> 0.25mV) of the input AC logic level table (Page 58) 2. Changed Setup/ Hold time (tDS/tDH, Page 67/68) Inserted IDD value at the IDD table of (-2, -22,-25) speed bin (Page 64) 1.