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HYMD116G725B8-K - Registered DDR SDRAM DIMM

Download the HYMD116G725B8-K datasheet PDF. This datasheet also covers the HYMD116G725B8-M variant, as both devices belong to the same registered ddr sdram dimm family and are provided as variant models within a single manufacturer datasheet.

Description

Hynix HYMD116G725B(L)8-M/K/H/L series is registered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 16Mx72 high-speed memory arrays.

Features

  • 128MB (16M x 72) Registered DDR DIMM based on 16Mx8 DDR SDRAM JEDEC Standard 184-pin dual in-line memory module (DIMM) Error Check Correction (ECC) Capability Registered inputs with one-clock delay Phase-lock loop (PLL) clock driver to reduce loading 2.5V +/- 0.2V VDD and VDDQ Power supply All inputs and outputs are compatible with SSTL_2 interface.
  • Fully dif.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HYMD116G725B8-M_HynixSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by SK Hynix

Part Number Description
HYMD116G725B8-H Registered DDR SDRAM DIMM
HYMD116G725B8-L Registered DDR SDRAM DIMM
HYMD116G725B8-M Registered DDR SDRAM DIMM
HYMD116G725BH8-M Registered DDR SDRAM DIMM
HYMD116G725BK8-M Registered DDR SDRAM DIMM

Full PDF Text Transcription

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www.DataSheet4U.com 16Mx72 bits Registered DDR SDRAM DIMM HYMD116G725B(L)8-M/K/H/L DESCRIPTION Hynix HYMD116G725B(L)8-M/K/H/L series is registered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules (DIMMs) which are organized as 16Mx72 high-speed memory arrays. Hynix HYMD116G725B(L)8-M/ K/H/L series consists of nine 16Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate. Hynix HYMD116G725B(L)8-M/K/H/L series provide a high performance 8-byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition. Hynix HYMD116G725B(L)8-M/K/H/L series is designed for high speed of up to 133MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs.
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