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HYMD116645DL8J - Unbuffered DDR SDRAM DIMM

Download the HYMD116645DL8J datasheet PDF. This datasheet also covers the HYMD116645D8J variant, as both devices belong to the same unbuffered ddr sdram dimm family and are provided as variant models within a single manufacturer datasheet.

Description

Hynix HYMD116645D(L)8J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules(DIMMs) which are organized as 16Mx64 high-speed memory arrays.

Features

  • 128MB (16M x 64) Unbuffered DDR DIMM based on 16Mx8 DDR SDRAM JEDEC Standard 184-pin dual in-line memory module (DIMM) 2.5V +/- 0.2V VDD and VDDQ Power supply 2.6V +/- 0.1V VDD and VDDQ Power supply for DDR400 All inputs and outputs are compatible with SSTL_2 interface Fully differential clock operations (CK & /CK) with 125MHz/133MHz/166MHz/200MHz All addresses and control inputs except Data, Data strobes and Data masks latche.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HYMD116645D8J_HynixSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by SK Hynix

Part Number Description
HYMD116645D8J Unbuffered DDR SDRAM DIMM
HYMD1166458-H 16Mx64 Unbuffered DDR Sdram Dimm
HYMD1166458-L 16Mx64 Unbuffered DDR Sdram Dimm
HYMD116645B8-H Unbuffered DDR SDRAM DIMM
HYMD116645B8-K Unbuffered DDR SDRAM DIMM

Full PDF Text Transcription

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16Mx64 bits Unbuffered DDR SDRAM DIMM HYMD116645D(L)8J DESCRIPTION Hynix HYMD116645D(L)8J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory Modules(DIMMs) which are organized as 16Mx64 high-speed memory arrays. Hynix HYMD116645D(L)8J series consists of eight 16Mx8 DDR SDRAM in 400mil TSOP II packages on a 184pin glass-epoxy substrate.Hynix HYMD116645D(L)8J series provide a high performance 8-byte interface in 5.25" width form factor of industry standard. It is suitable for easy interchange and addition. Hynix HYMD116645D(L)8J series is designed for high speed of up to 200MHz and offers fully synchronous operations referenced to both rising and falling edges of differential clock inputs.
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