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HY62256ALP-I - 32Kx8bit CMOS SRAM

Features

  • The Fully static operation and HY62256A/HY62256A-I Tri-state outputs is a high-speed, low TTL compatible inputs power and 32,786 x 8-bits and outputs CMOS Static Random Low power consumption Access Memory -2.0V(min. ) data fabricated using retention Hyundai's high Standard pin performance CMOS configuration process technology. The -28 pin 600 mil PDIP HY62256A/HY62256A-I -28 pin 330 mil SOP has a data retention mode -28 pin 8x13.4 mm that guarantees data to TSOP-1 remain valid at the (standard an.

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HY62256ALP 32K x 8-Bit CMOS SRAM Hyundai
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Full PDF Text Transcription

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Data Sheet-sram/62256ald1 http://www.hea.com/hean2/sram/62256ald1.htm HY62256A-(I) Series 32Kx8bit CMOS SRAM Description Features The Fully static operation and HY62256A/HY62256A-I Tri-state outputs is a high-speed, low TTL compatible inputs power and 32,786 x 8-bits and outputs CMOS Static Random Low power consumption Access Memory -2.0V(min.) data fabricated using retention Hyundai's high Standard pin performance CMOS configuration process technology. The -28 pin 600 mil PDIP HY62256A/HY62256A-I -28 pin 330 mil SOP has a data retention mode -28 pin 8x13.4 mm that guarantees data to TSOP-1 remain valid at the (standard and reversed) minimum power supply voltage of 2.0 volt. Using the CMOS technology, supply voltages from 2.0 to 5.
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