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HY5V26CLF - (HY5V26CxF) 4 Banks X 2M X 16bits Synchronous DRAM

Download the HY5V26CLF datasheet PDF. This datasheet also covers the HY5V26CF variant, as both devices belong to the same (hy5v26cxf) 4 banks x 2m x 16bits synchronous dram family and are provided as variant models within a single manufacturer datasheet.

Description

The Hynix HY5V26C(L/S)F is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth.

Features

  • Single 3.3±0.3V power supply All device balls are compatible with LVTTL interface 54Ball FBGA (10.5mm x 8.3mm) All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM or LDQM.
  • Internal four banks operation Programmable CAS Latency ; 2, 3 Clocks.
  • Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full page for.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HY5V26CF_HynixSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HY5V26CLF
Manufacturer SK Hynix
File Size 286.43 KB
Description (HY5V26CxF) 4 Banks X 2M X 16bits Synchronous DRAM
Datasheet download datasheet HY5V26CLF Datasheet

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Other Datasheets by SK Hynix

Part Number Description
HY5V26CF (HY5V26CxF) 4 Banks X 2M X 16bits Synchronous DRAM
HY5V26CSF (HY5V26CxF) 4 Banks X 2M X 16bits Synchronous DRAM
HY5V22F 4 Banks x 1M x 32Bit Synchronous DRAM
HY5V22FP 4 Banks x 1M x 32Bit Synchronous DRAM
HY5V22GF 4 Banks x 1M x 32Bit Synchronous DRAM

Full PDF Text Transcription

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www.DataSheet4U.com HY5V26C(L/S)F 4 Banks x 2M x 16bits Synchronous DRAM DESCRIPTION Preliminary The Hynix HY5V26C(L/S)F is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY5V26C(L/S)F is organized as 4banks of 2,097,152x16 HY5V26C(L/S)F is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
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