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HY5S5B6GLFP-SE - 256Mbit (16Mx16bit) Mobile SDR Memory

Download the HY5S5B6GLFP-SE datasheet PDF. This datasheet also covers the HY5S5B6GLF-6 variant, as both devices belong to the same 256mbit (16mx16bit) mobile sdr memory family and are provided as variant models within a single manufacturer datasheet.

Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HY5S5B6GLF-6_HynixSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by SK Hynix

Part Number Description
HY5S5B6GLFP-S 256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLFP-6 256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLFP-6E 256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLFP-H 256Mbit (16Mx16bit) Mobile SDR Memory
HY5S5B6GLFP-HE 256Mbit (16Mx16bit) Mobile SDR Memory

Full PDF Text Transcription

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256MBit MOBILE SDR SDRAMs based on 4M x 4Bank x16 I/O Specification of 256M (16Mx16bit) Mobile SDRAM Memory Cell Array - Organized as 4banks of 4,194,304 x16 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.0 / Apr. 2006 1 256Mbit (16Mx16bit) Mobile SDR Memory HY5S5B6GLF(P)-xE Series 11 Document Title 4Bank x 4M x 16bits Synchronous DRAM Revision History Revision No. 0.1 Initial Draft 1. Changed 166MHz IDD1 : 60mA --> 75mA 133MHz IDD1 : 55mA --> 65mA 105MHz IDD1 : 50mA --> 55mA 2. Remove CL2 operation (Page 13 to 14) 1. Release History Draft Date Feb. 2006 Remark Preliminary 0.2 Mar. 2006 Preliminary 1.0 Apr. 2006 Final Rev 1.
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