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HY5DU56822CF - (HY5DU56xxxC(L)F) 256M DDR SDRAM

Description

and is subject to change without notice.

Hynix semiconductor does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has two bytewide data strobes (UDQS, LDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL ali.

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Other Datasheets by SK Hynix

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HY5DU56822CT (HY5DU56xx22CT) 256M-P DDR SDRAM
HY5DU56822AT (HY5DU56xx22A(L)T) 256M-S DDR SDRAM
HY5DU56822BT-D4 (HY5DU56x22BT-D4x) 256M-P DDR SDRAM
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Full PDF Text Transcription

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w w w .D a t a e h S et 4U . m o c HY5DU56422C(L)F HY5DU56822C(L)F HY5DU561622C(L)F 256M DDR SDRAM HY5DU56422C(L)F HY5DU56822C(L)F HY5DU561622C(L)F w w w .D t a S a e h t e U 4 .c m o This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.1/ Nov. 2003 1 w w w .D at h S a t e e 4U . m o c HY5DU56422C(L)F HY5DU56822C(L)F HY5DU561622C(L)F Revision History Revision No. 0.1 History Define Preliminary Specification Draft Date Nov. 2003 Remark Rev. 0.1 / Nov.
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