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HY57V561620T - 4Banks x 4M x 16Bit Synchronous DRAM

Download the HY57V561620T datasheet PDF. This datasheet also covers the HY57V561620 variant, as both devices belong to the same 4banks x 4m x 16bit synchronous dram family and are provided as variant models within a single manufacturer datasheet.

Description

The HY57V561620T is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth.

HY57V561620 is organized as 4 banks of 4,194,304x16.

Features

  • Single 3.3V ± 0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM and LDQM Internal four banks operation.
  • Auto refresh and self refresh 8192 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 and Full Page for Sequential Burst.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HY57V561620_HynixSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HY57V561620T
Manufacturer SK Hynix
File Size 151.78 KB
Description 4Banks x 4M x 16Bit Synchronous DRAM
Datasheet download datasheet HY57V561620T Datasheet

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Other Datasheets by SK Hynix

Part Number Description
HY57V561620 4Banks x 4M x 16Bit Synchronous DRAM
HY57V561620BLT-I 4 Banks x 4M x 16Bit Synchronous DRAM
HY57V561620BT-I 4 Banks x 4M x 16Bit Synchronous DRAM
HY57V561620CLT 4 Banks x 4M x 16Bit Synchronous DRAM
HY57V561620CT 4 Banks x 4M x 16Bit Synchronous DRAM

Full PDF Text Transcription

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HY57V561620(L)T 4Banks x 4M x 16Bit Synchronous DRAM DESCRIPTION The HY57V561620T is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V561620 is organized as 4 banks of 4,194,304x16. The HY57V561620T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
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