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HY57V28820HCLT - 4Banks x 4M x 8bits Synchronous DRAM

Download the HY57V28820HCLT datasheet PDF. This datasheet also covers the HY57V28820HCT variant, as both devices belong to the same 4banks x 4m x 8bits synchronous dram family and are provided as variant models within a single manufacturer datasheet.

Description

The Hynix HY57V28820HC(L)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth.

HY57V28820HC(L)T is organized as 4banks of 4,194,304x8.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HY57V28820HCT-HynixSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by SK Hynix

Part Number Description
HY57V28820HCT 4Banks x 4M x 8bits Synchronous DRAM
HY57V28820HCT-L (HY57V28820HC(L)T-L) 4Banks x 4M x 8bits Synchronous DRAM
HY57V28820HLT-L (HY57V28820HC(L)T-L) 4Banks x 4M x 8bits Synchronous DRAM
HY57V281620A 4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620ELT Synchronous DRAM Memory

Full PDF Text Transcription

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HY57V28820HC(L)T 4Banks x 4M x 8bits Synchronous DRAM 0.1 : Hynix Change 0.2 : Burst read single write mode correction Rev. 0.2 / Aug. 2001 1 HY57V28820HC(L)T 4Banks x 4M x 8bits Synchronous DRAM DESCRIPTION The Hynix HY57V28820HC(L)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V28820HC(L)T is organized as 4banks of 4,194,304x8. HY57V28820HC(L)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
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