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HY57V283220TP - 4 Banks x 1M x 32Bit Synchronous DRAM

Download the HY57V283220TP datasheet PDF. This datasheet also covers the HY5V22F variant, as both devices belong to the same 4 banks x 1m x 32bit synchronous dram family and are provided as variant models within a single manufacturer datasheet.

Description

and is subject to change without notice.

Hynix Semiconductor Inc.

does not assume any responsibility for use of circuits described.

Features

  • JEDEC standard 3.3V power supply All device pins are compatible with LVTTL interface 86TSOP-II, 90Ball FBGA with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by DQM0,1,2 and 3.
  • Internal four banks operation.
  • Burst Read Single Write operation Programmable CAS Latency ; 2, 3 Clocks.
  • Auto refresh and self refresh 4096 refresh cycles /.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HY5V22F_HynixSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HY57V283220TP
Manufacturer SK Hynix
File Size 938.60 KB
Description 4 Banks x 1M x 32Bit Synchronous DRAM
Datasheet download datasheet HY57V283220TP Datasheet

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Other Datasheets by SK Hynix

Part Number Description
HY57V283220T 4 Banks x 1M x 32Bit Synchronous DRAM
HY57V283220LT 4 Banks x 1M x 32Bit Synchronous DRAM
HY57V283220LTP 4 Banks x 1M x 32Bit Synchronous DRAM
HY57V281620A 4 Banks x 2M x 16bits Synchronous DRAM
HY57V281620ELT Synchronous DRAM Memory

Full PDF Text Transcription

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www.DataSheet4U.com HY57V283220(L)T(P)/ HY5V22(L)F(P) 4 Banks x 1M x 32Bit Synchronous DRAM Revision History Revision No. 0.1 History Defined Preliminary Specification 1) 2) 3) 4) 5) 6) Modified FBGA Ball Configuration Typo. Changed Functional Block Diagram from A10 to A11. Changed VDD min from 3.0V to 3.135V. Changed Cap. Value from C11, 3, 5 to 4pf & C12, 3.8 to 4pf. Insert tAC2 Value. Insdrt tRAS & CLK Value. Remark 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Defined IDD Spec. Delited Preliminary. Changed IDD Spec. 133MHz Speed Added Changed FBGA Package Size from 11x13 to 8x13. 1) Changed VDD min from 3.135V to 3.0V. 2) Changed VIL min from VSSQ-0.3V to -0.3V. Modified of size erra. (Page15) (Equation : 13.00 ± 10 -> 13.00 ± 0.
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