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HY57V281620HCT - (HY57V281620HC(L/S)T) 4 Banks x 2M x 16-Bits SDRAM

Description

The Hynix HY57V281620HC(L/S)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth.

Features

  • Single 3.3±0.3V power supply All device pins are compatible with LVTTL interface JEDEC standard 400mil 54pin TSOP-II with 0.8mm of pin pitch All inputs and outputs referenced to positive edge of system clock Data mask function by UDQM or LDQM Internal four banks operation.
  • Auto refresh and self refresh 4096 refresh cycles / 64ms Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full page for Sequential Burst.
  • -.

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Datasheet Details

Part number HY57V281620HCT
Manufacturer SK Hynix
File Size 262.25 KB
Description (HY57V281620HC(L/S)T) 4 Banks x 2M x 16-Bits SDRAM
Datasheet download datasheet HY57V281620HCT Datasheet

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Full PDF Text Transcription

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( DataSheet : www.DataSheet4U.com ) 0.1 : Hynix Change 0.2 : 143Mhz Add, Burst read single write mode correction www.DataSheet4U.com www.DataSheet4U.com HY57V281620HC(L/S)T 4 Banks x 2M x 16bits Synchronous DRAM DESCRIPTION The Hynix HY57V281620HC(L/S)T is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V281620HC(L/S)T is organized as 4banks of 2,097,152x16 HY57V281620HC(L/S)T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
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