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H5RS5223CFR
512Mbit (16Mx32) GDDR3 SDRAM H5RS5223CFR
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied. Rev. 1.5 /Jul. 2008
1
H5RS5223CFR
Revision History
Revision Page
History
Date
Remark
0.1 Defined target spec.
Oct. 2007 Preliminary
0.2
Changed tCK_max to 2ns at (-N0) & PKG drawing value
Oct. 2007 Preliminary
0.3
1. Revised the slew rate from 6V/ns to 3V/ns on page 54.
Nov. 2007 Preliminary
2. Inserted the code ‘C’ in Part number, that means ‘normal power
and commercial temperature’.
0.4 Inserted 1.2Ghz speed bin
Dec. 2007 Preliminary
1.0 Added IDD Values
Jan. 2008
1.1 47 Changed IDDO/IDD1/IDD5A Values
Jan.
H5RS5223CFR Datasheet
