Datasheet4U Logo Datasheet4U.com

HD74SSTV16857 - 1:1 14-bit SSTL-2 Registered Buffer

Description

The HD74SSTV16857 is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.

Data flow from D to Q is controlled by differential clock pins (CLK, CLK) and the RESET.

Features

  • Supports LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input.
  • Differential SSTL_2 (Stub series terminated logic) CLK signal.
  • Flow through architecture optimizes PCB layout.
  • Package type Package type TSSOP-48 pin TVSOP-48 pin Package code TTP-48DB TTP-48DEV Package suffix T N Taping code EL (1,000 pcs / Reel) EL (1,000 pcs / Reel) HD74SSTV16857 Function Table Inputs RESET L H H H H: L: X: ↑: ↓: Note: CLK X ↓ ↓ L or H CLK X ↑ ↑ H or L D X H L X L.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
HD74SSTV16857 1:1 14-bit SSTL_2 Registered Buffer Renesas
HD74SSTV16857A 1:1 14-bit SSTL_2 Registered Buffer Renesas
HD74SSTV16857B 1:1 14-bit SSTL_2 Registered Buffer Renesas
HD7400 TTL HD74/HD74S Series Renesas Technology
HD7404 TTL Hex Inverters Renesas Technology

Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74AC00 Quad 2-Input NAND Gate
HD74AC02 Quad 2-Input NOR Gate
HD74AC04 Hex Inverter
HD74AC08 Quad 2-Input AND Gate
HD74AC107 Dual JK Flip-Flop (with Separate Clear and Clock)

Full PDF Text Transcription

Click to expand full text
www.DataSheet4U.com HD74SSTV16857 1:1 14-bit SSTL_2 Registered Buffer ADE-205-336F (Z) Rev.6 June. 2001 Description The HD74SSTV16857 is a 14-bit registered buffer designed for 2.3 V to 2.7 V Vcc operation and LVCMOS reset (RESET) input / SSTL_2 data (D) inputs and CLK input. Data flow from D to Q is controlled by differential clock pins (CLK, CLK) and the RESET. Data is triggered on the positive edge of the positive clock (CLK), and the negative clock (CLK) must be used to maintain noise margins. When RESET is low, all registers are reset and all outputs are low. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.
Published: |