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HD74LVC74 - Dual D-type Flip Flops with Preset and Clear

Description

The HD74LVC74 has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package.

The logic level present at the data input is transferred to the output during the positive going transition of the clock pulse.

Features

  • VCC = 2.0 V to 5.5 V All inputs VIH (Max. ) = 5.5 V (@VCC = 0 V to 5.5 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) High output current ±24 mA (@VCC = 3.0 V to 5.5 V) HD74LVC74 Function Table Inputs PR L H L H H H H H H: L: X: ↓: ↑: Q0: Note: CLR H L L H H H H H CK X X X ↑ ↑ L H ↓ D X X X H L X X X Outputs Q H L H H L Q0 Q0 Q0.
  • 1 Q L H H.
  • 1 L H Q0 Q0 Q0 High leve.

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📁 Similar Datasheet

Part Number Description Manufacturer
HD74LVC74 Dual D-type Flip Flops Renesas
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Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74LVC00 Quad. 2-input NAND Gates
HD74LVC02 Quad. 2-input NOR Gates
HD74LVC04 Hex Inverters
HD74LVC08 Quad. 2-input AND Gates
HD74LVC125A Quad. Bus Buffer Gates with 3-state Outputs

Full PDF Text Transcription

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HD74LVC74 Dual D-type Flip Flops with Preset and Clear ADE-205-066C(Z) Rev.3 September 1995 Description The HD74LVC74 has independent data, preset, clear, and clock inputs Q and Q outputs in a 14 pin package. The logic level present at the data input is transferred to the output during the positive going transition of the clock pulse. Preset and clear are independent of the clock and accomplished by a low level at the appropriate input. Low voltage and high speed operation is suitable at the battery drive product (note type personal computer) and low power consumption extends the life of a battery for long time operation. Features • • • • • VCC = 2.0 V to 5.5 V All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.
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