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HD74LVC373A - Octal D-type Transparent

Description

The HD74LVC373A has eight D type latches with three state outputs in a 20 pin package.

When the latch enable input is high, the Q outputs will follow the D inputs.

When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again.

Features

  • VCC = 2.0 V to 5.5 V All inputs VIH (Max. ) = 5.5 V (@V CC = 0 V to 5.5 V) All outputs VOUT (Max. ) = 5.5 V (@VCC = 0 V or output off state) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) High output current ±24 mA (@VCC = 3.0 V to 5.5 V) Function Table Inputs G H L L L H: L: X: Z: Q0 : LE X H H L D X L H X Output Q Z L H Q0 High level Low level Immaterial High impeda.

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📁 Similar Datasheet

Part Number Description Manufacturer
HD74LVC373A Octal D-type Transparent Latches Renesas
HD74LVC374A Octal D-type Flip Flops Renesas
HD74LVC32 Quad. 2-input OR Gates Renesas
HD74LVC00 Quad. 2-input NAND Gates Renesas
HD74LVC02 Quad. 2-input NOR Gates Renesas

Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74LVC374A Octal D-type Flip Flops
HD74LVC32 Quad. 2-input OR Gates
HD74LVC00 Quad. 2-input NAND Gates
HD74LVC02 Quad. 2-input NOR Gates
HD74LVC04 Hex Inverters

Full PDF Text Transcription

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HD74LVC373A Octal D-type Transparent Latches with 3-state Outputs ADE-205-112B(Z) 3rd Edition December 1996 Description The HD74LVC373A has eight D type latches with three state outputs in a 20 pin package. When the latch enable input is high, the Q outputs will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.
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