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HD74LV175A - Quad. D-type Flip-Flops with Clear

Description

Information at the D inputs of the HD74LV175A is transferred to the Q and Q outputs on the positive going edge of the clock pulse.

Both true and complement outputs from each flip-flop are externally available.

All four flip-flops are controlled by a common clock and common clear.

Features

  • VCC = 2.0 V to 5.5 V operation All inputs VIH (Max. ) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max. ) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) Function Table Inputs CLR L H H H Note: H: L: X: ↑: ↓: CLK X ↑ ↑ ↓ High level Low level Immaterial Low to high transiti.

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Other Datasheets by Hitachi Semiconductor (now Renesas)

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Full PDF Text Transcription

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HD74LV175A Quad. D-type Flip-Flops with Clear ADE-205-270 (Z) 1st Edition April 1999 Description Information at the D inputs of the HD74LV175A is transferred to the Q and Q outputs on the positive going edge of the clock pulse. Both true and complement outputs from each flip-flop are externally available. All four flip-flops are controlled by a common clock and common clear. Clearing is accomplished by a negative pulse at the clear input. All four Q outputs are cleared to a logic low level and all four Q outputs to a logic high level. Low-voltage and high-speed operation is suitable for battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life. Features • • • • • • VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.
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