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HD74HC85 - 4-Bit Magnitude Comparator

Description

The HD74HC85 id designed for high speed comparison of two four bit words.

This circuit has eight comparison input, 4 for each word; three cascade inputs (A < B, A > B, A = B); and three decision outputs (A < B, A > B, A = B).

Features

  • High Speed Operation: tpd (Data Word Input to Output) = 20 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) HD74HC85 Function Table Data Word Inputs A3, B3 A2, B2 A1, B1 X X X X A1 > B1 A1 < B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A1 = B1 A0, B0 X X X X X X A0 > B0 A0 < B0 A0 = B0 A0 = B.

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📁 Similar Datasheet

Part Number Description Manufacturer
HD74HC85 4-bit Magnitude Comparator Renesas
HD74HC83 4-bit Binary Full Adder Renesas
HD74HC86 Quad. 2-input Exclusive-OR Gates Renesas
HD74HC00 Quad. 2-input NAND Gates Renesas
HD74HC01 Quad. 2-input NAND Gates Renesas

Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74HC83 4-Bit Binary Full Adder
HD74HC86 Quad. 2-input Exclusive-OR Gates
HD74HC00 Quad. 2-input NAND Gates
HD74HC01 Quad. 2-input NAND Gates
HD74HC02 Quad. 2-input NOR Gates

Full PDF Text Transcription

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HD74HC85 4-Bit Magnitude Comparator Description The HD74HC85 id designed for high speed comparison of two four bit words. This circuit has eight comparison input, 4 for each word; three cascade inputs (A < B, A > B, A = B); and three decision outputs (A < B, A > B, A = B). The result of a comparison is indicated by a high level on one of the decision outputs. thus it may be determined whether one word is “greater than,” “less than,” or “equal to” the other word. by connecting the outputs of the least significant stage to the cascade inputs of the enxt stage, words of greater than four bits can be compared. In addition the least significant stage must have a high level applied to the A = B input, and a low level to the A < B, and A > B inputs.
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