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HD74HC563 - Octal Transparent Latches

Description

When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D inputs and the Q outputs of HD74HC573 will follow the D inputs.

When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again.

Features

  • High Speed Operation: tpd (Data to Q, Q) = 11 ns typ (CL = 50 pF) High Output Current: Fanout of 15 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Outputs Output Control L L L H Q0 : Q0 : Latch Enable H H L X Data H L X X HD74HC563 L H Q0 Z HD74HD573 H L Q0 Z level of Q before the indicated Steady-sate input conditions were establish.

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📁 Similar Datasheet

Part Number Description Manufacturer
HD74HC563 Octal Transparent Latches Renesas
HD74HC564 Octal D-type Flip-Flops Renesas
HD74HC564P Octal D-type Flip-Flops Renesas
HD74HC51 AND-OR-INVERT Gate Renesas
HD74HC533 Octal D-type Transparent Latches Renesas

Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74HC564 Octal D-type Flip-Flop
HD74HC564P Octal D-type Flip-Flop
HD74HC51 AND-OR-INVERT Gate
HD74HC533 Octal D-type Transparent Latches
HD74HC534 Octal D-type Flip-Flop

Full PDF Text Transcription

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HD74HC563/HD74HC573 Octal Transparent Latches (with 3-state outputs) Description When the latch enable (LE) input is high, the Q outputs of HD74HC563 will follow the inversion of the D inputs and the Q outputs of HD74HC573 will follow the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.
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