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HD74HC386 - Quad. 2-input Exclusive-OR Gates

Description

Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G is low.

Features

  • High Speed Operation: tpd = 13 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Function Table Inputs Enable G H L L X L Clock X Data X H L X Outputs Q Q0 H L Q0 Q Q0 L H Q0 HD74HC377 Pin Arrangement Enable G 1 1Q 2 1D 3 2D 4 2Q 5 3Q 6 3D 7 4D 8 4Q 9 GND 10 (Top view) Q D Q D 20 VCC 19 8Q 18 8D.

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📁 Similar Datasheet

Part Number Description Manufacturer
HD74HC386 Quad. 2-input Exclusive-OR Gates Renesas
HD74HC30 8-input NAND Gates Renesas
HD74HC32 Quad. 2-input OR Gates Renesas
HD74HC323 8-bit Universal Shift/Storage Register Renesas
HD74HC352 Dual 4-to-1-line Data Selectors/Multiplexers Renesas

Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74HC30 8-input NAND Gate
HD74HC32 Quad. 2-input OR Gates
HD74HC323 8-bit Universal Shift/Storage Register (with 3-state Outputs)
HD74HC352 Dual 4-to-1-line Data Selectors/Multiplexers
HD74HC353 Dual 4-to-1-line Data Selectors/Multiplexers (with 3-state outputs)

Full PDF Text Transcription

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HD74HC377 Octal D-type Flip-Flops (with Enable) Description Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse if the enable input G is low. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect at the output. The circuits are designed to prevent false clocking by transitions at the G input.
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