Datasheet4U Logo Datasheet4U.com

HD74HC373 - Octal D-type Transparent Latches

Description

When the latch enable input is high, the Q outputs of HD74HC373 will follow the D inputs and the Q outputs of HD74HC533 will follow the inversion of the D inputs.

When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again.

Features

  • High Speed Operation: tpd (D to Q) = 16 ns typ (CL = 50 pF).
  • High Output Current: Fanout of 15 LSTTL Loads.
  • Wide Operating Voltage: VCC = 2 to 6 V.
  • Low Input Current: 1 µA max.
  • Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C).
  • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation HD74HC373P HD74HC533P DILP-20 pin PRDP0020AC-B (DP-20NEV) P HD74HC373FPEL HD74HC533FPEL SOP-20.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
HD74HC373 Octal D-type Transparent Latches Renesas
HD74HC374 Octal D-type Flip-Flops Renesas
HD74HC375 Quad. Bistable Latches Renesas
HD74HC377 Octal D-type Flip-Flops Renesas
HD74HC30 8-input NAND Gates Renesas

Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74HC374 Octal D-type Flip-Flops (with 3-state outputs)/Octal D-type Flip-flops (with inverted 3-state outputs)
HD74HC375 Quad. Bistable Latches
HD74HC377 Octal D-type Flip-Flops (with Enable)
HD74HC30 8-input NAND Gate
HD74HC32 Quad. 2-input OR Gates

Full PDF Text Transcription

Click to expand full text
HD74HC373, HD74HC533 Octal D-type Transparent Latches (with 3-state outputs) Octal D-type Transparent Latches (with inverted 3-state outputs) REJ03D0619-0200 (Previous ADE-205-498) Rev.2.00 Mar 30, 2006 Description When the latch enable input is high, the Q outputs of HD74HC373 will follow the D inputs and the Q outputs of HD74HC533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.
Published: |