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HD74HC298 - Quad. 2-input Multiplexers (with storage)

Description

This circuit is controlled by the signals word select and clock.

When the word select input is taken low word 1 (A 1, B1, C1 and D 1) is presented to the inputs of the flip-flops, and when word select is high word 2 (A 2, B 2, C2 and D2) is presented to the inputs of the flip-flops.

Features

  • High Speed Operation: tpd (Clock to Q) = 19 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max Function Table Inputs Word Select L H X H Clock Outputs QA a1 a2 QA0 QB b1 b2 QB0 QC c1 c2 QC0 QD d1 d2 QD0 HD74HC298 Pin Arrangement B2 A2 A1 Data inputs B1 C2 D2 D1 GND 1 2 3 4 5 6 7 8 A2 A1 B1 C2 D2 D1 B2 QA QB Q.

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Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74HC292 Programmable Frequency Divider/Digital Timer
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Full PDF Text Transcription

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HD74HC298 Quad. 2-input Multiplexers (with storage) Description This circuit is controlled by the signals word select and clock. When the word select input is taken low word 1 (A 1, B1, C1 and D 1) is presented to the inputs of the flip-flops, and when word select is high word 2 (A 2, B 2, C2 and D2) is presented to the inputs of the flip-flops. The selected word is clocked to the output terminals on the negative edge of the clock pulse.
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