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HD74ALVCH16827 - 20-bit Buffers / Drivers with 3-state Outputs

Description

The HD74ALVCH16827 is composed of two 10-bit sections with separated output enable signals.

For either 10-bit buffer section, the two output enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be low for the corresponding Y outputs to be active.

Features

  • VCC = 2.3 V to 3.6 V.
  • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C).
  • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C).
  • High output current ±24 mA (@V CC = 3.0 V).
  • Bus hold on data inputs eliminates the need for external pullup / pulldown resistors Function Table Inputs OE1 L L H X H : High level L : Low level X : Immaterial Z : High impedance OE2 L L X H A L H X X L H Z Z Output Y HD74ALVCH16827 Pin Arrangement 1OE1 1 1Y1 2 1.

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Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74ALVCH16820 3.3-V 10-bit Flip Flops with Dual Outputs
HD74ALVCH16821 3.3-V 20-bit Bus Interface Flip Flops with 3-state Outputs
HD74ALVCH16825 18-bit Buffers / Drivers with 3-state Outputs
HD74ALVCH16830 1-bit to 2-bit Address Driver with 3-state Outputs
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HD74ALVCH16827 20-bit Buffers / Drivers with 3-state Outputs ADE-205-140B (Z) 3rd. Edition December 1999 Description The HD74ALVCH16827 is composed of two 10-bit sections with separated output enable signals. For either 10-bit buffer section, the two output enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be low for the corresponding Y outputs to be active. If either output enable input is high, the outputs of that 10-bit buffer section are in the high impedance state. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level. Features • VCC = 2.3 V to 3.6 V • Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) • Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25°C) • High output current ±24 mA (@V CC = 3.
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