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HD74AC195 - 4-bit Parallel-Access Shift Register

Description

This shift register

Features

  • parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a direct overriding clear. This shift register can operate in two modes: Parallel load; Shift from Q 0 towards Q3. Parallel loading is accomplished by applying the four bits of data, and taking the PE Input low. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the CP input. During parallel loading, serial data flow is inhibited. Serial shifting occurs s.

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📁 Similar Datasheet

Part Number Description Manufacturer
HD74AC195 4-bit Parallel-Access Shift Register Renesas
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Other Datasheets by Hitachi Semiconductor (now Renesas)

Part Number Description
HD74AC194 4-bit Bidirectional Unviersal Shift Register
HD74AC107 Dual JK Flip-Flop (with Separate Clear and Clock)
HD74AC112 Dual JK Negative Edge-Triggered Flip-Flop
HD74AC123A Dual Retriggerable Resettable Multivibrator
HD74AC125 Quad Buffer/Line Driver with 3-State Output

Full PDF Text Transcription

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HD74AC195 4-bit Parallel-Access Shift Register Description This shift register features parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a direct overriding clear. This shift register can operate in two modes: Parallel load; Shift from Q 0 towards Q3. Parallel loading is accomplished by applying the four bits of data, and taking the PE Input low. The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the CP input. During parallel loading, serial data flow is inhibited. Serial shifting occurs synchronously when the PE input is high. Serial data for this mode is entered at the J-K inputs. These inputs allow the first stage to perform as a J- K or toggle flip-flop as shown in the function table.
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