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HDMP-0421 - Port Bypass Circuits

Download the HDMP-0421 datasheet PDF. This datasheet also covers the HDMP-0421_Hewlett variant, as both devices belong to the same port bypass circuits family and are provided as variant models within a single manufacturer datasheet.

Description

The HDMP-0421 is a Single Port Bypass Circuit (PBC) with Clock and Data Recovery (CDR), and dual Signal Detect (SD) capability.

This configuration will control jitter accumulation while repeating incoming signals.

Features

  • Supports ANSI X3T11 1.0625 Gbps FC-AL Loop Configuration.
  • Supports 802.3z 1.25 Gbps Gigabit Ethernet (GE) Rates.
  • Single PBC, CDR, Dual Signal Detect (SD) in a Single Package.
  • Bidirectional, Symmetric Bypass Capability.
  • CDR in Bypass Path and Loop Path.
  • CDR Location Determined by Wiring Configuration of Pins on PCB (Patent Pending).
  • Envelope Detect on Cable Input (SD) for Both Directions.
  • Equalizers On All Inputs.
  • H.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HDMP-0421_Hewlett-Packard.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HDMP-0421
Manufacturer Hewlett-Packard
File Size 183.86 KB
Description Port Bypass Circuits
Datasheet download datasheet HDMP-0421 Datasheet

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Other Datasheets by Hewlett-Packard

Part Number Description
HDMP-0422 Single Port Bypass Circuit
HDMP-0440 Quad Port Bypass Circuit
HDMP-0450 Quad Port Bypass Circuit
HDMP-0452 Quad Port Bypass Circuit
HDMP-0480 Octal Cell Port Bypass Circuit without Clock and Data Recovery

Full PDF Text Transcription

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www.DataSheet4U.com Port Bypass Circuits for Fibre Channel Arbitrated Loop Standard and its Extensions Technical Data Features • Supports ANSI X3T11 1.0625 Gbps FC-AL Loop Configuration • Supports 802.3z 1.25 Gbps Gigabit Ethernet (GE) Rates • Single PBC, CDR, Dual Signal Detect (SD) in a Single Package • Bidirectional, Symmetric Bypass Capability • CDR in Bypass Path and Loop Path • CDR Location Determined by Wiring Configuration of Pins on PCB (Patent Pending) • Envelope Detect on Cable Input (SD) for Both Directions • Equalizers On All Inputs • High Speed PECL I/Os Referenced to VCC • Buffered Line Logic (BLL) Outputs without External Bias Resistors • 0.4 W Typical Power at VCC = 3.
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