GS8673ED36BK Datasheet | GSI Technology

GS8673ED18/36BK-675/625/550/500 260-Ball BGA mercial Temp Industrial Temp 72Mb SigmaQuad-IIIe™ Burst of 4 ECCRAM™ 675 MHz- 500 MHz 1.35V VDD 1.2V to 1.5V VDDQ Features - On-Chip ECC with virtually zero SER - Configurable Read Latency (3.0 or 2.0 cycles) - Simultaneous Read and Write SigmaQuad-IIIe™ Interface - Separate I/O Bus - Double Data Rate interface - Burst of 4 Read and Write - Pipelined read operation - Fully coherent Read and Write pipelines - 1.35V nominal VDD - 1.2V JESD8-16A BIC-3 pliant Interface - 1.5V HSTL Interface - ZQ pin for programmable output drive impedance - ZT pin for programmable input termination impedance - Configurable Input Termination - IEEE 1149.1 JTAG-pliant Boundary Scan - 260-ball, 14 mm x 22 mm, 1 mm ball pitch BGA package - K: 5/6 RoHS-pliant package - GK: 6/6 RoHS-pliant package SigmaQuad-IIIe™ Family Overview SigmaQuad-IIIe ECCRAMs are the Separate I/O half of the SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance ECCRAMs. Although very similar to GSI's second generation of networking SRAMs (the SigmaQuad-II/SigmaDDR-II family), these third generation devices offer several new Features that help enable significantly higher performance. Clocking and Addressing Schemes The GS8673ED18/36BK SigmaQuad-IIIe ECCRAMs are synchronous devices. They employ dual, single-ended master clocks, CK and CK. These clocks are single-ended clock inputs, not differential inputs to a single differential clock input buffer. CK and CK are used to control the address and control input registers, as well as all output timing. The KD and KD clocks are dual mesochronous (with respect to CK and CK) input clocks that are used to control the data input registers. Consequently, data input setup and hold windows can be optimized independently...