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33689D - SPI Controller

General Description

of each pin can be found in the Functional Pin Description section beginning on page 19.

7 8, 9, 24, 25 10 11 NC L1, L2 HS3

No internal connection to these pins.

Key Features

  • The device provides full SPIreadable diagnostics and a selectable timing watchdog for detecting errant operation. The LIN transceiver waveshaping circuitry can be disabled for higher data rates. One 50 mA and two 150 mA high side switches with output protection are available to drive inductive or resistive loads. The 150 mA switches can be pulse-width modulated (PWM). Two high voltage inputs are available for contact monitoring or as external wake-up inputs. A current sense operational amplifie.

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Full PDF Text Transcription for 33689D (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for 33689D. For precise diagrams, and layout, please refer to the original PDF.

Freescale Semiconductor Technical Data Document Number: MC33689 Rev. 8.0, 9/2012 System Basis Chip with LIN Transceiver 33689D The 33689 is a serial peripheral interface ...

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ith LIN Transceiver 33689D The 33689 is a serial peripheral interface (SPI) controlled system basis chip (SBC) that combines many frequently used functions in an MCU-based system plus a local interconnect network (LIN) transceiver. Applications include power window, mirror, and seat controls. The 33689 has a 5.0 V, 50 mA low dropout regulator with full protection and reporting features. The device provides full SPIreadable diagnostics and a selectable timing watchdog for detecting errant operation. The LIN transceiver waveshaping circuitry can be disabled for higher data rates.

More Datasheets from Freescale Semiconductor (now NXP Semiconductors)

Part Number Description
33660 ISO K Line Serial Link Interface
33662 LIN Physical Layer
33663 DUAL LIN TRANSCEIVER