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74VCX162601 - Low Voltage 18-Bit Universal Bus Transceivers

Download the 74VCX162601 datasheet PDF. This datasheet also covers the 74VCX variant, as both devices belong to the same low voltage 18-bit universal bus transceivers family and are provided as variant models within a single manufacturer datasheet.

General Description

The VCX162601, 18-bit universal bus transceiver, combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs.

Key Features

  • s 1.65V.
  • 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s 26Ω series resistors in B-Port outputs s tPD (A to B) 3.8 ns max for 3.0V to 3.6V VCC 4.6 ns max for 2.3V to 2.7V VCC 9.2 ns max for 1.65V to 1.95V VCC s Power-down high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s Static Drive (IOH/IOL B outputs) ±12 mA @ 3.0V VCC ±8 mA @ 2.3V VCC ±3 mA @ 1.65V VCC s Uses patented noise/EMI reduction circuitry s Latchup performance exceeds 300 mA s ESD.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74VCX-162601.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74VCX162601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26Ω Series Resistors in the B-Port Outputs April 1998 Revised April 1999 74VCX162601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26Ω Series Resistors in the B-Port Outputs General Description The VCX162601, 18-bit universal bus transceiver, combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH.