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74LVTH32373 - Low Voltage 32-Bit Transparent Latch

Download the 74LVTH32373 datasheet PDF. This datasheet also covers the 74LVT32373 variant, as both devices belong to the same low voltage 32-bit transparent latch family and are provided as variant models within a single manufacturer datasheet.

General Description

The LVT32373 and LVTH32373 contain thirty-two noninverting latches with 3-STATE outputs and are intended for bus oriented applications.

The device is byte controlled.

The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH.

Key Features

  • s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH32373), also available without bushold feature (74LVT32373) s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink.
  • 32 mA/+64 mA s ESD performance: Human-body model > 2000V Machine model > 200V Charged-device model > 1000V s Packaged in plastic Fine-Pitch Ball.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74LVT32373_FairchildSemiconductor.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Preliminary 74LVT32373 • 74LVTH32373 Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs (Preliminary) August 2001 Revised August 2001 74LVT32373 • 74LVTH32373 Low Voltage 32-Bit Transparent Latch with 3-STATE Outputs (Preliminary) General Description The LVT32373 and LVTH32373 contain thirty-two noninverting latches with 3-STATE outputs and are intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in a high impedance state.