Datasheet4U Logo Datasheet4U.com

74ALVCR162601 - Low Voltage 18-Bit Universal Bus Transceivers

General Description

The 74ALVCR162601, 18-bit universal bus transceiver, combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Key Features

  • I 1.65.
  • 3.6V VCC supply operation I 3.6V tolerant inputs and outputs I 26Ω series resistors on both the A and B Port outputs. I tPD (A to B, B to A) 4.3 ns max for 3.0V to 3.6V VCC 5.1 ns max for 2.3V to 2.7V VCC 9.2 ns max for 1.65V to 1.95V VCC I Power-down HIGH impedance inputs and outputs I Supports live insertion/withdrawal (Note 1) I Uses patented noise/EMI reduction circuitry I Latchup conforms to JEDEC JED78 I ESD performance: Human body model > 2000V Machine model >200V Note 1: T.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
74ALVC00 Low Voltage Quad 2-Input NAND Gate ON Semiconductor
74ALVC00 Quad 2-input NAND gate nexperia
74ALVC00-Q100 Quad 2-input NAND gate nexperia
74ALVC02 Quad 2-input NOR gate NXP
74ALVC02 Quad 2-input NOR gate nexperia

Other Datasheets by Fairchild (now onsemi)

Part Number Description
74ALVC00 Low Voltage Quad 2-Input NAND Gate
74ALVC08 Low Voltage Quad 2-Input AND Gate
74ALVC132 Low Voltage Quad 2-Input NAND Gate
74ALVC162240 Low Voltage 16-Bit Inverting Buffer/Line Driver
74ALVC162244 Low Voltage 16-Bit Buffer/Line Driver

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74ALVCR162601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26Ω Series Resistors in the Outputs September 2001 Revised October 2001 74ALVCR162601 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs and 26Ω Series Resistors in the Outputs General Description The 74ALVCR162601, 18-bit universal bus transceiver, combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH.