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74ALVCF322835 - Low Voltage 36-Bit Universal Bus Driver

General Description

The 74ALVCF322835 low voltage 36-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes.

Data flow is controlled by output-enable (OE), latch-enable (LE), and clock (CLK) inputs.

Key Features

  • s Compatible with PC133 DIMM module specifications s 1.65V to 3.6V VCC specifications provided s 3.6V tolerant outputs s 26Ω series resistors in outputs s tPD (CLK to O n) 3.7 ns max for 3.0V to 3.6V VCC 4.6 ns max for 2.3V to 2.7V VCC 7.4 ns max for 1.65V to 1.95V VCC s Power-down high impedance outputs s Latchup conforms to JEDEC JED78 s ESD performance: Human body model > 2000V Machine model >200V Ordering Code: Order Number 74ALVCF322835G (Note 1) (Note 2) Package Number BGA114A Package Des.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74ALVCF322835 Low Voltage 36-Bit Universal Bus Driver with 3.6V Tolerant Outputs and 26Ω Series Resistors in Outputs May 2002 Revised May 2002 74ALVCF322835 Low Voltage 36-Bit Universal Bus Driver with 3.6V Tolerant Outputs and 26Ω Series Resistors in Outputs General Description The 74ALVCF322835 low voltage 36-bit universal bus driver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched and clocked modes. Data flow is controlled by output-enable (OE), latch-enable (LE), and clock (CLK) inputs. The device operates in Transparent Mode when LE is held HIGH. The device operates in clocked mode when LE is LOW and CLK is toggled. Data transfers from the Inputs (In) to Outputs (On) on a Positive Edge Transition of the Clock.