Datasheet4U Logo Datasheet4U.com

74ALVC16500 - Low Voltage 18-Bit Universal Bus Transceivers

General Description

The ALVC16500 is an 18-bit universal bus transceiver which combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Key Features

  • s 1.65V.
  • 3.6V VCC supply operation s 3.6V tolerant inputs and outputs s tPD (A to B, B to A) 3.4 ns max for 3.0V to 3.6V VCC 4.0 ns max for 2.3V to 2.7V VCC 7.0 ns max for 1.65V to 1.95V VCC s Power-off high impedance inputs and outputs s Supports live insertion/withdrawal (Note 1) s Uses patented noise/EMI reduction circuitry s Latchup conforms to JEDEC JED78 s ESD performance: Human body model > 2000V Machine model >200V Note 1: To ensure the high-impedance state during power up or powe.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
74ALVC162244 Low-Voltage 16-Bit Buffer/Line Driver ON Semiconductor
74ALVC162334A 16-bit registered driver NXP
74ALVC162334A 16-bit registered driver nexperia
74ALVC162334ADGG 16-bit registered driver nexperia
74ALVC16240 Low-Voltage 1.8/2.5/3.3V 16-Bit Buffer ON Semiconductor

Other Datasheets by Fairchild (now onsemi)

Part Number Description
74ALVC16501 Low Voltage 18-Bit Universal Bus Transceivers
74ALVC162240 Low Voltage 16-Bit Inverting Buffer/Line Driver
74ALVC162244 Low Voltage 16-Bit Buffer/Line Driver
74ALVC162245 Low Voltage 16-Bit Bidirectional Transceiver
74ALVC162373 Low Voltage 16-Bit Transparent Latch

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74ALVC16500 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs October 2001 Revised October 2001 74ALVC16500 Low Voltage 18-Bit Universal Bus Transceivers with 3.6V Tolerant Inputs and Outputs General Description The ALVC16500 is an 18-bit universal bus transceiver which combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level.