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74ACTQ273 - Quiet Series Octal D-Type Flip-Flop

Description

The ACTQ273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs.

The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously.

The register is fully edge-triggered.

Features

  • GTO output control and undershoot corrector in addition to a split ground bus for superior performance. Features s ICC reduced by 50% s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Improved latch-up immunity s Buffered common clock and asynchronous master reset s Outputs source/sink 24 mA s 4 kV minimum ESD immunity Ordering Code: Order Number 74ACTQ273SC 74ACTQ273SJ 74ACTQ273MTC 74ACTQ273PC Package Number M20B M.

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Full PDF Text Transcription

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74ACTQ273 Quiet Series Octal D-Type Flip-Flop August 1989 Revised November 1999 74ACTQ273 Quiet Series Octal D-Type Flip-Flop General Description The ACTQ273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) input load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each Dtype input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.
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