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XRK79892 - INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER

Description

The XRK79892 is a PLL clock driver designed specifically for redundant clock tree designs.

The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs.

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Full PDF Text Transcription

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www.DataSheet4U.com xr JANAUARY 2005 PRELIMINARY XRK79892 REV. P1.0.1 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER phase/frequency alignment will occur with minimal output phase disturbance. The typical phase bump caused by a failed clock is eliminated. FEATURES GENERAL DESCRIPTION The XRK79892 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals from which it generates 5 new differential LVPECL clock outputs. Two of the output pairs regenerate the input signals frequency and phase while the other three pairs generate 4x, phase aligned clock outputs. External PLL feedback is used to also provide zero delay buffer performance.
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