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EUP7998 - Sink/Source DDR Termination Regulator

General Description

The EUP7998 is a high performance linear regulator designed to provide power for termination of a DDR memory bus.

It significantly reduces parts count, board space and overall system cost over previous switching solutions.

Key Features

  • z z z z z z z z z z z VLDOIN Input Voltage Range: 1.1V to 3.5V VIN Input Voltage Range: 2.375V to 5.5V Typically 3 × 10μF MLCCs stable for DDR Fast Load-Transient Response ±10mA Buffered Reference (REFOUT) Meet DDR, DDR2 JEDEC Specifications. Supports DDR3 and Low-Power DDR3/DDR4 VTT.

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Datasheet Details

Part number EUP7998
Manufacturer Eutech
File Size 276.00 KB
Description Sink/Source DDR Termination Regulator
Datasheet download datasheet EUP7998 Datasheet

Full PDF Text Transcription for EUP7998 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for EUP7998. For precise diagrams, and layout, please refer to the original PDF.

EUP7998 Sink/Source DDR Termination Regulator DESCRIPTION The EUP7998 is a high performance linear regulator designed to provide power for termination of a DDR memory bus...

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egulator designed to provide power for termination of a DDR memory bus. It significantly reduces parts count, board space and overall system cost over previous switching solutions. The EUP7998 maintains a fast transient response using only 20μF or 30μF output capacitance. The EUP7998 supports a remote sensing function and all power requirements for DDR, DDR2, DDR3 and Low Power DDR3/DDR4 VTT bus termination. The EUP7998 provides current and thermal limits to prevent damage to the linear regulator. Additionally, The EUP7998 generates an open-drain PGOOD signal to monitor the output regulation. An active high enable pin EN c

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