EM44CM1688LBC
Features
- JEDEC Standard VDD/VDDQ = 1.8V±0.1V.
- All inputs and outputs are patible with SSTL_18 interface.
- Fully differential clock inputs (CK, /CK) operation.
- Eight Banks
- Posted CAS
- Bust length: 4 and 8.
- Programmable CAS Latency (CL): 5, 6
- Programmable Additive Latency (AL): 0, 1, 2, 3, 4, 5
- Write Latency (WL) =Read Latency (RL) -1.
- Read Latency (RL) = Programmable Additive
Latency (AL) + CAS Latency (CL)
- Bi-directional Differential Data Strobe (DQS).
- Data inputs on DQS centers when write.
- Data outputs on DQS, /DQS edges when read.
- On chip DLL align DQ, DQS and /DQS transition with CK transition.
- DM mask write data-in at the both rising and falling edges of the data strobe.
- Sequential & Interleaved Burst type available.
- Off-Chip Driver (OCD) Impedance Adjustment
- On Die Termination (ODT)
- Auto Refresh and Self Refresh
- 8,192 Refresh Cycles / 64ms
- Average Refresh Period 7.8us at lower than Tcase 85
°C, 3.9us at 85°C < Tcase ≦ 95°C
- Ro HS pliance
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