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DM2M32SJ - 2Mbx32 Enhanced DRAM SIMM

Download the DM2M32SJ datasheet PDF. This datasheet also covers the DM2M36SJ variant, as both devices belong to the same 2mbx32 enhanced dram simm family and are provided as variant models within a single manufacturer datasheet.

General Description

The Enhanced Memory Systems 8MB EDRAM SIMM module provides a single memory module solution for the main memory or local memory of fast PCs, workstations, servers, and other high performance systems.

Key Features

  • Architecture s 4KByte SRAM Cache Memory for 12ns Random Reads Within Two Active Cache Pages s Fast DRAM Array for 30ns Access to Any New Page s Write Posting Register for 12ns Random Writes and Burst Writes Within a Page (Hit or Miss) s 2KByte Wide DRAM to SRAM Bus for 113.6 Gigabytes/Sec Cache Fill s On-chip Cache Hit/Miss Comparators Maintain Cache Coherency on Writes s Hidden Precharge and Refresh Cycles s Extended 64ms Refresh Period for Low Standby Power s Standard CMOS/TTL Compatible I/O.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DM2M36SJ-EnhancedMemorySystems.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number DM2M32SJ
Manufacturer Enhanced Memory Systems
File Size 203.97 KB
Description 2Mbx32 Enhanced DRAM SIMM
Datasheet download datasheet DM2M32SJ Datasheet

Other Datasheets by Enhanced Memory Systems

Part Number Description
DM2M36SJ 2Mbx36 Enhanced DRAM SIMM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Enhanced Memory Systems Inc. DM2M36SJ/DM2M32SJ 2Mbx36/2Mbx32 Enhanced DRAM SIMM Product Specification Features Architecture s 4KByte SRAM Cache Memory for 12ns Random Reads Within Two Active Cache Pages s Fast DRAM Array for 30ns Access to Any New Page s Write Posting Register for 12ns Random Writes and Burst Writes Within a Page (Hit or Miss) s 2KByte Wide DRAM to SRAM Bus for 113.6 Gigabytes/Sec Cache Fill s On-chip Cache Hit/Miss Comparators Maintain Cache Coherency on Writes s Hidden Precharge and Refresh Cycles s Extended 64ms Refresh Period for Low Standby Power s Standard CMOS/TTL Compatible I/O Levels and +5 or 3.