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V370PDC - High Performance PCI SDRAM Controller with Integrated Peripheral Control Unit

General Description

Table 2 below lists the pin types found on the V370PDC.

Table 3 describes the function of each pin on the V370PDC.

Pin Type PCI I PCI O PCI I/O PCI I/OD I/O8 I/OD I O2 O8 O12 PCI input only pin.

Key Features

  • multiple address translation units from PCI which allow designers the freedom to customize their local address space. Access latency of slower peripherals are absorbed through the large OnChip FIFOs. The peripheral bus provides low latency access to SDRAM. The peripheral control unit on the V370PDC also performs address decoding and chip-select strobes generation for SRAM, PROM and other slow peripherals. The peripheral bus can also be tri-stated through a simple hand-shaking protocol to allow o.

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Datasheet Details

Part number V370PDC
Manufacturer Unknown Manufacturer
File Size 99.35 KB
Description High Performance PCI SDRAM Controller with Integrated Peripheral Control Unit
Datasheet download datasheet V370PDC Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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V370PDC Rev. A0 High Performance PCI SDRAM Controller with Integrated Peripheral Control Unit • Fully compliant with PCI 2.2 specification target interface • Multiplexed or Non-multiplexed 8-, 16-, or 32-bit generic peripheral bus interface • Support up to 1 Gbyte of SDRAM • Support up to 2 single banks or 1 dual bank industrial standard 168-pin PC SDRAM DIMM • Support up to 1Kbyte of burst access from PCI • Up to 5 programmable chip select for peripheral strobe generation • Large On-Chip FIFOs using V3’s unique DYNAMIC BANDWIDTH ALLOCATION™ architecture • Buffered PCI clock output • Hot Swap Ready (PICMG™ Hot Swap Specification) • Implementation of PCI Bus Power Management Interface Specification Version 1.