74LS107
Description
This device contains two independent negative-edge-triggered J-K flip-flops with plementary outputs The J and K data is processed by the flip-flops on the falling edge of the clock pulse The clock triggering occurs at a voltage level and is not directly related to the transition time of the negative going edge of the clock pulse The data on the J and K inputs may change while the clock is high or low without affecting the outputs as long as setup and hold times are not violated A low logic level on the clear input will reset the outputs regardless of the logic levels of the other inputs
Connection Diagram
Dual-In-Line Package
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TL F 6367
- 1
Order Number DM54LS107AJ DM54LS107AW DM74LS107AM or DM74LS107AN See NS Package Number J14A M14A N14A or W14B
Function Table
Inputs CLR L H H H H H CLK X J X L H L H X K X L L H H X Q L Q0 H L Toggle Q0 Q0 Outputs Q H Q0 L H v v v v
H e High Logic Level X e Either Low or High Logic Level L e Low Logic Level v e Negative going...
