M15F2G16128A-EFBG2L - 16M x 16 Bit x 8 Banks DDR3 SDRAM

Product Overview

ESMT

Part number	M15F2G16128A-EFBG2L
Manufacturer	ESMT
File Size	3.70 MB
Description	16M x 16 Bit x 8 Banks DDR3 SDRAM
Datasheet	M15F2G16128A-EFBG2L Datasheet
Additional preview pages of the M15F2G16128A-EFBG2L datasheet.

The 2Gb Double-Data-Rate-3 (DDR3) DRAM is double data rate architecture to achieve high-speed operation.

and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages. DDR3 SDRAM Addressing Configuration 128Mb x16 # of Bank 8 Bank Address BA0.

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Published: Apr 18, 2019 |