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CY9DF126 - Cluster Arm Cortex-R4 MCU

Datasheet Summary

Description

CY9DF126 series is based on Cypress’s advanced Arm architecture (32-bit with instruction pipeline for RISC-like performance).

Improvements compared to the previous generation include significantly improved performance at higher frequency, reduced power consumption and faster start-up time.

Features

  • High-Performance/High Memory Content.
  • Arm® Cortex®-R4, 8KB D-Cache, 8KB I-Cache.
  • 32-Bit Armv7 architecture.
  • 205 DMIPS.
  • 2MB Internal Flash.
  • 64KB Internal EEFlash (Data Flash).
  • 208KB Internal RAM with ECC Connectivity.
  • 3x CAN, 2 x LIN-USART, 3 x SPI, 1 x I2C, 2 x I2S.
  • Up to six Stepper Motor Control (SMC) outputs.
  • HS-SPI (memory mapped access).
  • APIX 1 x PHY / 2 x AIC.
  • External Bus Interface (24-bit address/16-bit data) Safety Features/Securit.

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Datasheet preview – CY9DF126

Datasheet Details

Part number CY9DF126
Manufacturer Cypress
File Size 1.94 MB
Description Cluster Arm Cortex-R4 MCU
Datasheet download datasheet CY9DF126 Datasheet
Additional preview pages of the CY9DF126 datasheet.

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CY9DF126 - Atlas CY9DF126 Series General Description CY9DF126 series is based on Cypress’s advanced Arm architecture (32-bit with instruction pipeline for RISC-like performance). Improvements compared to the previous generation include significantly improved performance at higher frequency, reduced power consumption and faster start-up time. For highest processing speed at optimized power consumption an internal PLL can be selected to supply the CPU with up to 128 MHz operation frequency from an external resonator. Note Arm, Cortex, Thumb and CoreSight are the trademarks of Arm Limited in the EU and other countries. Note APIX® is a registered mark of INOVA Semiconductors GmbH.
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