Datasheet4U Logo Datasheet4U.com

CY7B8392 - Low Power Ethernet Coaxial Transceiver

Download the CY7B8392 datasheet PDF. This datasheet also covers the CY7B8392-1 variant, as both devices belong to the same low power ethernet coaxial transceiver family and are provided as variant models within a single manufacturer datasheet.

Description

It is possible, through the use of repeaters, to combine several networks together.

These networks can be a single Physical layer, i.e., only 10BASE2 or only 10BASE5, or it can by a combination of many different Ethernet physical layers.

Features

  • signal is necessary before it can be amplified and sent to the DTE. The CY7B8392 receiver circuitry has.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CY7B8392-1_Cypress.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
CY7B131 (CY7B131 / CY7B141) 1K x 8 Dual Port SRAM Cypress Semiconductor
CY7B134 (CY7B134 / CY7B135 / CY7B1342) 4K x 8 Dual Port SRAM Cypress Semiconductor
CY7B1342 (CY7B134 / CY7B135 / CY7B1342) 4K x 8 Dual Port SRAM Cypress Semiconductor
CY7B135 (CY7B134 / CY7B135 / CY7B1342) 4K x 8 Dual Port SRAM Cypress Semiconductor
CY7B136 (CY7B136 / CY7B146) SRAM Cypress Semiconductor

Other Datasheets by Cypress (Infineon)

Part Number Description
CY7B8392 Ethernet Coax Transceiver Interface
CY7C008 64K/128K x 8/9 Dual-Port Static RAM
CY7C008V 3.3V 64K/128K x 8/9 Dual-Port Static RAM
CY7C009 64K/128K x 8/9 Dual-Port Static RAM
CY7C009V 128K x 8 Dual-Port Static RAM

Full PDF Text Transcription

Click to expand full text
CY7B8392 Low Power Ethernet Coaxial Transceiver Application This application note describes the differences between the 10BASE5 (Ethernet) and 10BASE2 (Cheapernet) versions of the IEEE 802.3 standard, and provides guidelines for design with the CY7B8392. Data is sent out over the network in packets. An Ethernet packet consists of the preamble, destination address, source address, length field, data, and a Cyclic Redundancy Check (CRC). Each packet can be viewed as a sequence of 8-bit bytes, with the least significant bit of each byte being transmitted first. A typical Ethernet packet is shown in Figure 3. The preamble contains 8 bytes of alternating ones and zeros, ending with two consecutive ones. The preamble allows the receiving PLS to synchronize its clock with the sender.
Published: |