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CYWB0224ABS - West Bridge Astoria

Download the CYWB0224ABS datasheet PDF. This datasheet also covers the CYWB0224ABM variant, as both devices belong to the same west bridge astoria family and are provided as variant models within a single manufacturer datasheet.

Description

Clock/SPI clock Chip Enable/NAND Chip Select/SPI Slave Select Address Bus 0/PNAND Command Latch Address Bus 1/PNAND Ready_Buy Addr.

Bus [3:2] Addr.

Bus 4/NAND Write Protect Address Bus 5/I2C clock Address Bus 6/I2C data Addr.

Features

  • Pseudo CRAM interface (Antioch Interface) Pseudo NAND Flash interface SPI (slave mode) interface DMA slave support N-Xpress™ NAND Controller Technology.
  • Interleave up to 16 NANDs with 8 Chip Enables (CE#) for x8 or x16 SLC (CYWB0224ABS) or MLC (CYWB0224ABM) NAND flash devices. 4-bit Error Correction Coding Bad Block Management Static Wear Leveling Ultra low power, 1.8V core operation Low Power Modes Small footprint, 6x6mm VFBG.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CYWB0224ABM_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Cypress (Infineon)

Part Number Description
CYWB0224ABS USB and Mass Storage Peripheral Controller
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Full PDF Text Transcription

Click to expand full text
ADVANCE INFORMATION CYWB0224ABS/CYWB0224ABM TM TM West Bridge Astoria Features ■ ❐ ❐ ❐ ❐ ■ ■ ■ ■ ■ Pseudo CRAM interface (Antioch Interface) Pseudo NAND Flash interface SPI (slave mode) interface DMA slave support N-Xpress™ NAND Controller Technology ❐ Interleave up to 16 NANDs with 8 Chip Enables (CE#) for x8 or x16 SLC (CYWB0224ABS) or MLC (CYWB0224ABM) NAND flash devices. 4-bit Error Correction Coding Bad Block Management Static Wear Leveling Ultra low power, 1.8V core operation Low Power Modes Small footprint, 6x6mm VFBGA Supports I2C boot and Processor Boot Selectable Clock Input Frequencies ❐ ❐ ❐ ❐ ■ www.DataSheet4U.
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