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CYF2036V - 18/36/72-Mbit Programmable Multi-Queue FIFOs

Download the CYF2036V datasheet PDF. This datasheet also covers the CYF2018V variant, as both devices belong to the same 18/36/72-mbit programmable multi-queue fifos family and are provided as variant models within a single manufacturer datasheet.

Description

The Cypress programmable FIFO family offers the industry’s highest-density programmable FIFO memory device.

It has independent read and write ports, which can be clocked up to 100 MHz.

User can configure input and output bus sizes.

Features

  • Functional.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CYF2018V_CypressSemiconductor.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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Other Datasheets by Cypress (Infineon)

Part Number Description
CYF2018V 18/36/72-Mbit Programmable Multi-Queue FIFOs
CYF2072V 18/36/72-Mbit Programmable Multi-Queue FIFOs
CYF0018V 18/36/72 Mbit Programmable FIFOs
CYF0036V 18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO
CYF0072V 18/36/72 Mbit Programmable FIFOs Master reset to clear entire FIFO

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
CYF2018V, CYF2036V CYF2072V 18/36/72-Mbit Programmable Multi-Queue FIFOs 18/36/72-Mbit Programmable Multi-Queue FIFOs Features ■ Functional Description The Cypress programmable FIFO family offers the industry’s highest-density programmable FIFO memory device. It has independent read and write ports, which can be clocked up to 100 MHz. User can configure input and output bus sizes. The maximum bus size of 36 bits enables a maximum data throughput of 3.6 Gbps. The read and write ports can support multiple I/O voltage standards. The user-programmable registers enable user to configure the device operation as desired. The device also offers a simple and easy-to-use interface to reduce implementation and debugging efforts, improve time-to-market, and reduce engineering costs.
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